Author(s): Mr. Sunil Jadhav, Prof. Sachin Borse

There are so many strategies implemented to reduce the power consumption in CMOS digital design. Many of them are based on complement form and clock signals. In CMOS digital design power consumption can be reduced by reducing the supply voltage, decreasing capacitance and reducing the switching activities. These techniques are not suitable in today’s CMOS design scenario. So many researchers are working on new design techniques which will help in reducing the dynamic power consumption. Most of the research is focused on Adiabatic logic which is proved to be the excellent technique to design the low power digital circuits. In this paper we focus on the adiabatic logic with complementary energy path dual pass transistor logic (DPL-CEPAL). Conventional NAND, NOR and EX-OR/NOR gates are compared with the DPL-CEPAL NAND, NOR and EX-OR/NOR gates. It is proved that DPL-CEPAL technique is superior to conventional technology as far as power consumption is concerned. This DPL-CEPAL technology can be used to design the full adder cell and multiplier cell which are the core part of any ALU processor.